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publication order number: mmft2n02el/d ? semiconductor components industries, llc, 2000 november, 2000 rev. 4 1 mmft2n02el preferred device power mosfet 2 amps, 20 volts nchannel sot223 this power mosfet is designed to withstand high energy in the avalanche and commutation modes. this device is also designed with a low threshold voltage so it is fully enhanced with 5 volts. this new energy efficient device also offers a draintosource diode with a fast recovery time. designed for low voltage, high speed switching applications in power supplies, dcdc converters and pwm motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. the device is housed in the sot223 package which is designed for medium power surface mount applications. ? silicon gate for fast switching speeds ? low drive requirement to interface power loads to logic level ics, v gs(th) = 2 volts max ? the sot223 package can be soldered using wave or reflow. the formed leads absorb thermal stress during soldering, eliminating the possibility of damage to the die maximum ratings (t a = 25 c unless otherwise noted) rating symbol value unit draintosource voltage v ds 20 vdc gatetosource voltage continuous v gs 15 vdc drain current continuous drain current pulsed i d i dm 1.6 6.4 adc total power dissipation @ t a = 25 c derate above 25 c p d (note 1.) 0.8 6.4 watts mw/ c operating and storage temperature range t j , t stg 65 to 150 c single pulse draintosource avalanche energy starting t j = 25 c (v dd = 10 v, v gs = 5 v, peak i l = 2 a, l = 0.2 mh, r g = 25 w ) e as 66 mj thermal characteristics thermal resistance junctiontoambient (surface mounted) r q ja 156 c/w maximum temperature for soldering purposes, time in solder bath t l 260 10 c sec 1. power rating when mounted on fr4 glass epoxy printed circuit board using recommended footprint. 2 amperes 20 volts r ds(on) = 150 m d g s 1 2 3 4 nchannel device package shipping ordering information mmft2n02elt1 sot223 1000 tape & reel to261aa case 318e style 3 http://onsemi.com lww marking diagram 2n02l l = location code ww = work week pin assignment preferred devices are recommended choices for future use and best overall value. 3 2 1 4 gate drain source drain
mmft2n02el http://onsemi.com 2 electrical characteristics (t a = 25 c unless otherwise noted) characteristic symbol min typ max unit off characteristics draintosource breakdown voltage, (v gs = 0, i d = 250 m a) v (br)dss 20 vdc zero gate voltage drain current, (v ds = 20 v, v gs = 0) i dss 10 m adc gatebody leakage current, (v gs = 15 v, v ds = 0) i gss 100 nadc on characteristics gate threshold voltage, (v ds = v gs , i d = 1 ma) v gs(th) 1 2 vdc static draintosource onresistance, (v gs = 5 v, i d = 0.8 a) r ds(on) 0.15 ohms draintosource onvoltage, (v gs = 5 v, i d = 1.6 a) v ds(on) 0.32 vdc forward transconductance, (v ds = 10 v, i d = 0.8 a) g fs 2.6 mhos dynamic characteristics input capacitance (v ds = 15 v, c iss 580 output capacitance (v ds = 15 v , v gs = 0, f1mh) c oss 430 pf reverse transfer capacitance gs f = 1 mhz) c rss 250 switching characteristics turnon delay time t d(on) 16 rise time (v dd = 15 v, i d = 1.6 a v gs =5v r g = 50 ohms t r 73 ns turnoff delay time v gs = 5 v, r g = 50 ohms, r gs = 25 ohms) t d(off) 77 ns fall time r gs 25 ohms) t f 107 total gate charge (v ds = 16 v, i d = 1.6 a, q g 20 gatesource charge (v ds = 16 v , i d = 1 . 6 a , v gs = 5 vdc) sfi 15d16 q gs 1.7 nc gatedrain charge gs see figures 15 and 16 q gd 6 source drain diode characteristics (note 2.) forward onvoltage i s = 1.6 a, v gs = 0 v sd 0.9 vdc forward turnon time i s = 1.6 a, v gs = 0, dl s /dt = 400 a/ m s t on limited by stray inductance reverse recovery time dl s /dt = 400 a/ m s, v r = 16 v t rr 55 ns 2. pulse test: pulse width 300 m s, duty cycle 2%
mmft2n02el http://onsemi.com 3 typical electrical characteristics r ds(on) , drain-to-source resistance (ohms) r ds(on) , drain-to-source resistance (ohms) r ds(on) , drain-to-source resistance (ohms) 10 figure 1. on region characteristics v ds , drain-to-source voltage (volts) t j = 25 c 10 figure 2. gatethreshold voltage variation with temperature t j , junction temp ( c) figure 3. transfer characteristics v gs , gate-to-source voltage (volts) figure 4. onresistance versus drain current i d , drain current (amps) figure 5. onresistance versus gatetosource voltage v gs , gate-to-source voltage (volts) figure 6. onresistance versus junction temperature t j , junction temperature ( c) v ds = v gs i d = 1 ma i d , drain current (amps) 8 6 4 2 0 5 4 3 2 1 0 v gs(th) , gate threshold voltage (normalized) 1.1 -50 1 0.9 0.8 0.7 0 50 100 150 v ds = 8 v i d , drain current (amps) 8 6 2 0 7 6 4 2 0 0.3 0 0.2 0.15 0.1 0 123 4 t j = -55 c 100 c 25 c 0.25 -55 c 0.5 0.4 0.3 0.1 0 8 6 5 4 3 2 0.3 -50 0.1 0 0 50 100 150 0.4 0.2 7 4 0.05 0.5 0.2 7 6 5 4.5 4 3.5 3 t j = 100 c 25 c t j = 25 c i d = 1.6 a v gs = 5 v i d = 1.6 a v gs = 5 v 1.2 v gs = 2.5 v
mmft2n02el http://onsemi.com 4 forward biased safe operating area the fbsoa curves define the maximum draintosource voltage and drain current that a device can safely handle when it is forward biased, or when it is on, or being turned on. because these curves include the limitations of simultaneous high voltage and high current, up to the rating of the device, they are especially useful to designers of linear systems. the curves are based on an ambient temperature of 25 c and a maximum junction temperature of 150 c. limitations for repetitive pulses at various ambient temperatures can be determined by using the thermal response curves. on semiconductor application note, an569, atransient thermal resistancegeneral data and its useo provides detailed instructions. switching safe operating area the switching safe operating area (soa) is the boundary that the load line may traverse without incurring damage to the mosfet. the fundamental limits are the peak current, i dm and the breakdown voltage, bv dss . the switching soa is applicable for both turnon and turnoff of the devices for switching times less than one microsecond. figure 7. maximum rated forward biased safe operating area v gs = 15 v single pulse t a = 25 c 1 s 20ms dc 10 i d , drain current (amps) 0.1 1 0.1 0.01 1 10 100 v ds , drain-to-source voltage (volts) 100 ms 500ms r ds(on) limit thermal limit package limit 1.0 0.1 0.001 1.0e-05 1.0e-04 1.0e-03 1.0e-02 1.0e-01 1.0e+00 r(t), effective thermal resistance t, time (s) 0.1 0.01 0.2 0.02 0.01 d = 0.5 single pulse (normalized) 0.05 r q ja (t) = r(t) r q ja r q ja = 156 c/w max d curves apply for power pulse train shown read time at t 1 t j(pk) - t a = p (pk) r q ja (t) p (pk) t 1 t 2 duty cycle, d = t 1 /t 2 1.0e+01 figure 8. thermal response commutating safe operating area (csoa) the commutating safe operating area (csoa) of figure 10 defines the limits of safe operation for commutated sourcedrain current versus rea pplied drain voltage when the sourcedrain diode has undergone forward bias. the curve shows the limitations of i fm and peak v ds for a given rate of change of source current. it is applicable when waveforms similar to those of figure 9 are present. full or halfbridge pwm dc motor controllers are common applications requiring csoa data. device stresses increase with increasing rate of change of source current so di s /dt is specified with a maximum value. higher values of di s /dt require an appropriate derating of i fm , peak v ds or both. ultimately di s /dt is limited primarily by device, package, and circuit impedances. maximum device stress occurs during t rr as the diode goes from conduction to reverse blocking. v ds(pk) is the peak draintosource voltage that the device must sustain during commutation; i fm is the maximum forward sourcedrain diode current just prior to the onset of commutation. v r is specified at 80% rated bv dss to ensure that the csoa stress is maximized as i s decays from i rm to zero. r gs should be minimized during commutation. t j has only a second order effect on csoa. stray inductances in on semiconductor's test circuit are assumed to be practical minimums. dvds/dt in excess of 10 v/ns was attained with di s /dt of 400 a/ m s.
mmft2n02el http://onsemi.com 5 r g t v ds l i l v dd figure 9. commutating waveforms t p bv dss v dd i l(t) t, (time) figure 10. commutating safe operating area (csoa) 15 v v gs 0 90% i fm dl s /dt i s 10% t rr t frr 0.25 i rm i rm t on v ds v f v dsl v r v ds(pk) max. csoa stress area figure 11. commutating safe operating area test circuit + - + - figure 12. unclamped inductive switching test circuit v r v gs i fm 20 v r gs dut i s l i v r = 80% of rated v dss v dsl = v f + l i ? dl s /dt figure 13. unclamped inductive switching waveforms v ds , drain-to-source voltage (volts) i s , source current (amps) 10 0 9 8 7 6 0 4 8 12 16 30 2 6 10 14 18 5 4 3 2 1 20 22 24 26 28 di s /dt 400 a/ m s v ds
mmft2n02el http://onsemi.com 6 figure 14. capacitance variation with voltage same devicetype as dut v in +18v v dd 5v 100k 0.1 m f ferrite bead dut 100 2n3904 2n3904 47k 15v 100k v in = 15 v pk ; pulse width 100 m s, duty cycle 10%. 1ma 47k figure 15. gate charge versus gatetosource voltage gate-to-source or drain-to-source voltage (volts) c, capacitance (pf) c rss c iss c oss 1800 20 1600 800 600 400 200 0 15 5 0 5 10 15 20 figure 16. gate charge test circuit q g , total gate charge (nc) 10 0 9 8 7 0 520 v gs , gate-to-source voltage (volts) 6 5 4 2 10 15 1400 1200 1000 3 1 v gs v ds t j = 25 c f = 1 mhz t j = 25 c v ds = 16 v i d = 1.6 a c iss c rss c oss 10
mmft2n02el http://onsemi.com 7 information for using the sot223 surface mount package minimum recommended footprint for surface mounted applications surface mount board layout is a critical portion of the total design. the footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. with the correct pad geometry, the packages will self align when subjected to a solder reflow process. 0.079 2.0 0.15 3.8 0.248 6.3 0.079 2.0 0.059 1.5 0.059 1.5 0.059 1.5 0.091 2.3 0.091 2.3 mm inches sot223 power dissipation the power dissipation of the sot223 is a function of the drain pad size. this can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. power dissipation for a surface mount device is determined by t j(max) , the maximum rated junction temperature of the die, r q ja , the thermal resistance from the device junction to ambient, and the operating temperature, t a . using the values provided on the data sheet for the sot223 package, p d can be calculated as follows: p d = t j(max) t a r q ja the values for the equation are found in the maximum ratings table on the data sheet. substituting these values into the equation for an ambient temperature t a of 25 c, one can calculate the power dissipation of the device which in this case is 800 milliwatts. p d = 150 c 25 c 156 c/w = 800 milliwatts the 156 c/w for the sot223 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 800 milliwatts. there are other alternatives to achieving higher power dissipation from the sot223 package. one is to increase the area of the drain pad. by increasing the area of the drain pad, the power dissipation can be increased. although one can almost double the power dissipation with this method, one will be giving up area on the printed circuit board which can defeat the purpose of using surface mount technology. a graph of r q ja versus drain pad area is shown in figure 17.
mmft2n02el http://onsemi.com 8 0.8 watts 1.25 watts* 1.5 watts r , thermal resistance, junction to ambient (c/w) q ja a, area (square inches) 0.0 0.2 0.4 0.6 0.8 1.0 160 140 120 100 80 figure 17. thermal resistance versus drain pad area for the sot223 package (typical) board material = 0.0625 g-10/fr-4, 2 oz copper t a = 25 c *mounted on the dpak footprint another alternative would be to use a ceramic substrate or an aluminum core board such as thermal clad . using a board material such as thermal clad, an aluminum core board, the power dissipation can be doubled using the same footprint. solder stencil guidelines prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. a solder stencil is required to screen the optimum amount of solder paste onto the footprint. the stencil is made of brass or stainless steel with a typical thickness of 0.008 inches. the stencil opening size for the sot223 package should be the same as the pad size on the printed circuit board, i.e., a 1:1 registration. soldering precautions the melting temperature of solder is higher than the rated temperature of the device. when the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. ? always preheat the device. ? the delta temperature between the preheat and soldering should be 100 c or less.* ? when preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. when using infrared heating with the reflow soldering method, the difference shall be a maximum of 10 c. ? the soldering temperature and time shall not exceed 260 c for more than 10 seconds. ? when shifting from preheating to soldering, the maximum temperature gradient shall be 5 c or less. ? after soldering has been completed, the device should be allowed to cool naturally for at least three minutes. gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. ? mechanical stress or shock should not be applied during cooling * soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device.
mmft2n02el http://onsemi.com 9 typical solder heating profile for any given circuit board, there will be a group of control settings that will give the desired heat pattern. the operator must set temperatures for several heating zones, and a figure for belt speed. taken together, these control settings make up a heating aprofileo for that particular circuit board. on machines controlled by a computer, the computer remembers these profiles from one operating session to the next. figure 18 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. this profile will vary among soldering systems but it is a good starting point. factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. this profile shows temperature versus time. the line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. the two profiles are based on a high density and a low density board. the vitronics smd310 convection/infrared reflow soldering system was used to generate this profile. the type of solder used was 62/36/2 tin lead silver with a melting point between 177189 c. when this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. the components on the board are then heated by conduction. the circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. step 1 preheat zone 1 arampo step 2 vent asoako step 3 heating zones 2 & 5 arampo step 4 heating zones 3 & 6 asoako step 5 heating zones 4 & 7 aspikeo step 6 vent step 7 cooling 200 c 150 c 100 c 5 c time (3 to 7 minutes total) t max solder is liquid for 40 to 80 seconds (depending on mass of assembly) 205 to 219 c peak at solder joint desired curve for low mass assemblies desired curve for high mass assemblies 100 c 150 c 160 c 170 c 140 c figure 18. typical solder heating profile
mmft2n02el http://onsemi.com 10 package dimensions style 3: pin 1. gate 2. drain 3. source 4. drain h s f a b d g l 4 123 0.08 (0003) c m k j dim a min max min max millimeters 0.249 0.263 6.30 6.70 inches b 0.130 0.145 3.30 3.70 c 0.060 0.068 1.50 1.75 d 0.024 0.035 0.60 0.89 f 0.115 0.126 2.90 3.20 g 0.087 0.094 2.20 2.40 h 0.0008 0.0040 0.020 0.100 j 0.009 0.014 0.24 0.35 k 0.060 0.078 1.50 2.00 l 0.033 0.041 0.85 1.05 m 0 10 0 10 s 0.264 0.287 6.70 7.30 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. sot223 (to261) case 318e04 issue k
mmft2n02el http://onsemi.com 11 notes
mmft2n02el http://onsemi.com 12 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information central/south america: spanish phone : 3033087143 (monfri 8:00am to 5:00pm mst) email : onlitspanish@hibbertco.com tollfree from mexico: dial 018002882872 for access then dial 8662979322 asia/pacific : ldc for on semiconductor asia support phone : 3036752121 (tuefri 9:00am to 1:00pm, hong kong time) toll free from hong kong & singapore: 00180044223781 email : onlitasia@hibbertco.com japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mmft2n02el/d thermal clad is a registered trademark of the bergquist company. north america literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com fax response line: 3036752167 or 8003443810 toll free usa/canada n. american technical support : 8002829855 toll free usa/canada europe: ldc for on semiconductor european support german phone : (+1) 3033087140 (monfri 2:30pm to 7:00pm cet) email : onlitgerman@hibbertco.com french phone : (+1) 3033087141 (monfri 2:00pm to 7:00pm cet) email : onlitfrench@hibbertco.com english phone : (+1) 3033087142 (monfri 12:00pm to 5:00pm gmt) email : onlit@hibbertco.com european tollfree access*: 0080044223781 *available from germany, france, italy, uk, ireland

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